AP3843 datasheet

http://photos.utsource.net/gif/utsource1.gifproduct details:http://www.utsource.net/AP3843.htmlIf you want to buy this product please visit:http://www.utsource.net/ic-datasheet...3-1143571.htmlPopular search:AP3843 datasheetAP3843 buyAP3843 pinoutAP3843 data„ Features� Optimized for Off-Line and DC to DC Converters� Low Start-Up Current (�.5mA)� Automatic Feed Forward Compensation� Pulse-by-Pulse Current Limiting� Enhanced Load Response Characteristics� Under-Voltage Lockout (UVLO) with Hysteresis� Double Pulse Suppression� High Current Totem Pole Output� Internally Trimmed Bandgap Reference� Current Mode Operation to 500KHZ� Low Ro Error Amplifier�Pin ConnectionsPDIP-8L, SOP-8LTop View�General DescriptionThe AP3842/3/4/5 family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include under voltage lockout featuring start-up current less than 0.5 mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off-state.Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The AP3842 and AP3844 have UVLO thresholds of 16V(on) and 10V(off), ideally suited for off-line applications. The correspondingCOMP. 1ISENSE 3RT/CT 48 VREF6 OUTPUT5 GROUNDthresholds for the AP3843 and AP3845 are 8.5Vand 7.6V. The AP3842 and AP3843 can operate to duty cycles approaching 100%. A range of the zero to < 50% is obtained by the AP3844 and AP3845 by the addition of an internal toggle flip flop which�Ordering InformationAP 384X X X XPart No.PackageS8:SOP-8LLead FreeBlank : NormalPackingBlank: TubeN8:PDIP-8LL : Lead Free Package A : Taping�Block Diagram ( toggle flip flop used only in AP3844 and AP3845 )S/R 5V REFVREF GOOD LOGICINTERNAL BIAS5V 50mACURRENTERROR AMP.2R S R R1V CURRENTSENSE COMPARATORPWM LATCH�Absolute Maximum RatingsParameterSupply Voltage (low impedance source)Supply Voltage (li < 30mA)Self LimitingOutput CurrentOutput Energy (capacitive load)Analog Inputs (pins2,3)-0.3 to 5.5Error Amplifier Output Sink CurrentPower Dissipation at Tamb �00C (PDIP8)Power Dissipation at Tamb �5 C (SOP8)Storage Temperature Range-65 to 150Lead Temperature (soldering 10s)*Notes: 1. All voltages are with respect to pin 5, all currents are positive into the specified terminal.„ Electrical Characteristics(Unless otherwise stated, these specifications apply for 0≦Tamb�0 C for AP384X ; Vi = 15V(note 5); RT = 10K�CT = 3.3nF)AP384XParameterTest ConditionsREFERENCE SECTIONOutput VoltageTj = 250C I0=1mALine Regulation12V≦Vi�5VLoad Regulation1mA≦Io�0mA∆VREF/∆TTemperature Stability(Notes 2)Total Output VariationLine, Load, Temperature (Notes 2)Output Noise Voltage10Hz≦f�0KHz Tj=250C (NotesLong Term StabilityTamb=125 C, 1000Hrs (Notes 2)Output Short Circuit current„ Electrical Characteristics(Continued)(Unless otherwise stated, these specifications apply for 0≦T �0oC for AP384X ; V = 15V(note 5); R = 10K�C = 3.3nF)Notes�.These parameters, although guaranteed, are not 100% tested in production.3.Parameter measured at trip point of latch with VPIN2=0.4.Gain defined as:A= ∆VPIN1 PIN3�.8V5.Adjust Vi above the start threshold before setting at 15V.6.Output frequency equals oscillator frequency for the AP3842 and AP3843.7.Output frequency is one and half oscillator frequency for the AP3844 and AP3845.Figure 1 : Error Amp Configuration.Zf VFB 2COMP Zf 1Error amp can source or sink up to 0.5mAFigure 2 : Under Voltage Lockout.ON/OFF COMMAND TO REST OF ICAP3842 AP3843AP3844 AP3845VOFF VONDuring Under-Voltage Lockout, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents.Figure 3 : Current Sense Circuit.AMP 2RCURRENT3 SENSE C5 GNDR 1V CURRENT SENSECOMPARATORPeak current(is) is determined by the formulaIS max � 1.0V A small RC filter may be required to suppress switch transients.Figure 4.VREF 8RT/CT 4GROUND 5for R > 5K� f= 1.72Figure 5 : Open Loop Test Circuit.ERROR AMP. ADJUSTISENSE 5K ADJUST1 COMP.2 VFB3 ISENSEVREF 8OUTPUT 60.1 TWuF 1KHigh peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass apacitors should be connected close to pin 5 in a single point ground. The transistor and 5 K�potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.Figure 6 : Shutdown Techniques.B VREF1 COMPSHUTDOWN3 ISENSESHUTDOWNTO CURRENT SENSE RESISTORShutdown of the AP3842 can be accomplished in two ways; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either one of them causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR that will be reset by cycling Vi below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.Figure 7 : Slope Compensation.Uref 80.1uF RTRT/CT 4Isense 3R2 IsenseAP3842/3A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes.�Package Diagrams(1) PDIP-8L (Plastic Dual-in-line Package)E-PIN O0.118 inch15 (4X)PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch7 (4X)Dimensions in millimetersDimensions in inches(2) SOP-8L (JEDEC Small Outline Package)VIEW "A"7 (4X)0.015x457 (4X)VIEW "A"Dimensions In MillimetersDimensions In Inches0.0075„ Marking InformationPart No.AP384XB YYWW X X2,3,4,5Blank: normalL: Lead Free PackageID code: internalXth Week : 01~52Year : "01"=2001"02"=2002